In this section, you will create an AXI4-Lite compliant slave peripheral IP.
Create a new project as described in Creating a New Embedded Project with Zynq SoC.
With the Vivado design open, select Tools → Create and Package New IP. Click Next to continue.
Select Create a new AXI4 peripheral and then click Next.
Fill in the peripheral details as follows:
Screen
System Property
Setting or Comment to Use
Peripheral Details
Name
Blink
Version
1.0
Display name
Blink_v1.0
Description
My new AXI IP
IP location
C:/designs/ip_repro
Overwrite
existing unchecked
Click Next.
In the Add Interfaces page, accept the default settings and click Next.
In the Create Peripheral page, select Edit IP and then click Finish. Upon completion of the new IP generation process, the Package IP window opens (see the following figure).
In the Hierarchy view of the Sources window, right-click blink_v1_0 under the Design Sources folder and select Open File. You need to add Verilog code that creates output ports to map to the external LEDs on the ZC702 board. Navigate to the line
//Users to add ports here
and addoutput wire \[3:0\] leds
below this line, as shown in the following example://Users to add ports here output wire [3:0] leds, //User ports ends
Find the instantiation to the AXI bus interface and add
.leds(leds)
, as shown in the following example, to map the port connections:.S_AXI_RREADY(s00_axi_rready), .leds(leds) );
Save and close blink_v1_0.v.
Under Sources → Hierarchy → Design Sources→ blink_v1_0, right-click blink_v1_0_S00_AXI_inst - blink_v1_0_S00_AXI and select Open File.
Next, you will need to add Verilog code that creates output ports to map to the external LEDs on the ZC702 board and also create the logic code to blink the LEDs when register 0 is written to.
Navigate to the line
//Users to add ports here
and addoutput wire \[3:0\] leds
below this line, as shown in the example below://Users to add ports here output wire [3:0] leds, //User ports ends
Find the AXI4-Lite signals section:
// AXI4LITE signals reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr; reg axi_awready; reg axi_wready; reg [1 : 0] axi_bresp; reg axi_bvalid; reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr; reg axi_arready; reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata; reg [1 : 0] axi_rresp; reg axi_rvalid;
After this section, add a custom register, which you will use as a counter. Add the following code:
// add 28-bit register to use as counter reg [27:0] count;
Find the I/O connections assignments section:
// I/O Connections assignments assign S_AXI_AWREADY = axi_awready; assign S_AXI_WREADY = axi_wready; assign S_AXI_BRESP = axi_bresp; assign S_AXI_BVALID = axi_bvalid; assign S_AXI_ARREADY = axi_arready; assign S_AXI_RDATA = axi_rdata; assign S_AXI_RRESP = axi_rresp; assign S_AXI_RVALID = axi_rvalid;
Add the following code at the bottom:
// assign MSB of count to LEDs assign leds = count[27:24];
Toward the bottom of the file, find the section that states
Add user logic here
. Add the following code, which will increment the count while the slv_reg0 is set to 0x1. If the register is not set, the counter will not increment.// Add user logic here // on positive edge of input clock always @( posedge S_AXI_ACLK ) begin //if reset is set, set count = 0x0 if ( S_AXI_ARESETN == 1'b0 ) begin count <= 28'b0; end else begin //when slv_reg_0 is set to 0x1, increment count if (slv_reg0 == 2'h01) begin count <= count+1; end else begin count <= count; end end end // User logic ends
Save and close blink_v1_0_S00_AXI.v.
Open the Package IP - blink page. Under Packaging Steps, select Ports and Interfaces.
Click the Merge Changes from Ports and Interfaces Wizard link.
Make sure that the window is updated and includes the LEDs output ports.
Under Packaging Steps, select Review and Package. At the bottom of the Review and Package page, click Re-Package IP.
The view that opens states that packaging is complete and asks if you would like to close the project.
Click Yes.
Note
The custom core creation process that you have worked through is very simple with the example Verilog included in the IP creation process. For more information, refer to the GitHub Zynq Cookbook: How to Run BFM Simulation web page.