Connecting an AXI4-Lite Compliant Custom Slave IP - 2023.2 English

In this section, you will connect the AXI4-Lite compliant custom slave peripheral IP that you created in Creating Peripheral IP.

1. Open the Vivado project you previously created in Example 1: Creating a New Embedded Project with Zynq SoC.

2. Add the custom IP to the existing design. Right-click the Diagram view and select Add IP.

3. Type “blink” into the search view. Blink_v1.0 appears. Double-click the IP to add it to the design.

4. Click Run Connection Automation to make automatic port connections.

5. With the All Automation box checked by default, click OK to make the connections. Your new IP is automatically connected, but the leds output port is disconnected.

6. Right-click the leds port and select Make External.

   

7. In the Flow Navigator view, navigate to RTL Analysis and select Open Elaborated Design.

8. Click OK.

9. After the elaborated design opens, click the I/O Ports window and expand All ports → led_0.

   

10. Edit the leds port settings as follows:

    Port Name	I/O Std	Package Pin
    Leds[3]	LVCMOS25	P17
    Leds[2]	LVCMOS25	P18
    Leds[1]	LVCMOS25	W10
    Leds[0]	LVCMOS25	V7

    The following figure shows the completed leds port settings in the I/O Ports window.

    

11. Select Generate Bitstream.

12. The Save Project view opens. Ensure that the check box is selected and then click Save.

13. If a message appears stating that synthesis is Out-of-date, click Yes.

14. After the bitstream generation completes, export the hardware and launch the Vitis unified software platform.