Temperature Cycling Test - Temperature Cycling Test - UG116

Device Reliability Report (UG116)
Document_ID
UG116
Release_Date
2026-09-23
Revision
10.21 English

The temperature cycling test is conducted under the conditions of predefined maximum and minimum temperatures and in air-to-air environment. Package precondition is performed on the testing samples prior to the temperature cycling test.

Summary

Table 1. Summary of Temperature Cycling Test Results
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3Sxxx TCB 4 0 170 210,000
XC3SxxxE TCB 9 0 385 527,500
XC5VxXxxx TCB 4 0 180 202,500
XC6Sxxx TCB 6 0 265 437,400
XC6VxXxxx TCB 5 0 203 272,000
7 series FPGAs and Zynq 7000 SoCs TCB 11 0 489 804,000
UltraScale devices TCB, TCG 10 0 450 540,000
UltraScale+ devices TCB, TCG 21 0 909 1,537,500
Versal devices TCB, TCG, TCK 9 0 349 503,400

Data

Table 2. TC Test Results for XC3Sxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3S1000 TCB 4 0 170 210,000
XC3Sxxx TCB 4 0 170 210,000
Table 3. TC Test Results for XC3SxxxE
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC3S1200E TCB 2 0 80 160,000
XC3S250E TCB 3 0 130 150,000
XC3S500E TCB 4 0 175 217,500
XC3SxxxE TCB 9 0 385 527,500
Table 4. TC Test Results for XC5VxXxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC5VLX110T TCB 4 0 180 202,500
XC5VxXxxx TCB 4 0 180 202,500
Table 5. TC Test Results for XC6Sxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC6SLX150T TCB 2 0 105 117,400
XC6SLX45 TCB 4 0 160 320,000
XC6Sxxx TCB 6 0 265 437,400
Table 6. TC Test Results for XC6VxXxxx
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC6VLX240T TCB 4 0 178 222,000
XC6VSX475T TCB 1 0 25 50,000
XC6VxXxxx TCB 5 0 203 272,000
Table 7. TC Test Results for 7 series FPGAs and Zynq 7000 SoCs
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XC7A100T TCB 4 0 170 210,000
XC7Z020 TCB 7 0 319 594,000
7 series FPGAs and Zynq 7000 SoCs TCB 11 0 489 804,000
Table 8. TC Test Results for UltraScale devices
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XCKU040 TCB 7 0 315 382,500
XCVU095 TCB 3 0 135 157,500
UltraScale devices TCB, TCG 10 0 450 540,000
Table 9. TC Test Results for UltraScale+ devices
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XCVU13P TCG 4 0 179 246,000
XCVU19P TCG 2 0 50 67,500
XCZU19EG TCB 1 0 45 67,500
XCZU3EG TCB 9 0 408 816,000
XCZU9EG TCB 5 0 227 340,500
UltraScale+ devices TCB, TCG 21 0 909 1,537,500
Table 10. TC Test Results for Versal devices
Device Stress Condition Lot Quantity Fail Quantity Device Quantity Total Device Cycles
XCVC1702 TCB 1 0 45 67,500
XCVC1902 TCB 5 0 221 310,500
XCVP1702 TCG 1 0 30 30,000
XCVP1902 TCK 2 0 53 95,400
Versal devices TCB, TCG, TCK 9 0 349 503,400