The HAST test is conducted under the conditions of 130°C, 85% RH and VDD bias or
110°C, 85% RH and VDD bias. Package preconditioning is performed on the
testing samples prior to the HAST test.
Summary
Table 1. Summary of High Accelerated Stress Test Results
| Device |
Stress Condition |
Lot Quantity |
Fail Quantity |
Device Quantity |
Total Device Cycles |
| XC6Sxxx |
110°C / 85%RH |
4 |
0 |
178 |
93,984 |
| 7 series FPGAs and Zynq 7000 SoCs |
110°C / 85%RH |
12 |
0 |
538 |
272,184 |
Data
Table 2. HAST Test Results for XC6Sxxx
| Device |
Stress Condition |
Lot Quantity |
Fail Quantity |
Device Quantity |
Total Device Cycles |
| XC6SLX45 |
110°C / 85%RH |
4 |
0
|
178 |
93,984 |
| XC6Sxxx |
110°C / 85%RH |
4 |
0
|
178 |
93,984 |
Table 3. HAST Test Results for 7 series FPGAs and Zynq 7000 SoCs
| Device |
Stress Condition |
Lot Quantity |
Fail Quantity |
Device Quantity |
Total Device Cycles |
| XC7A35T |
110°C / 85%RH |
4 |
0
|
180 |
83,160 |
| XC7Z020 |
110°C / 85%RH |
8 |
0
|
358 |
189,024 |
| 7 series FPGAs and Zynq 7000 SoCs |
110°C / 85%RH |
12 |
0
|
538 |
272,184 |