The Zynq flat design has programmable logic (PL), and you want to defer the PL loading till Linux comes up, use the following steps to extract the PL bitstream and pack the dtbo and bitstream files into the /lib/firmware/xilinx directory in the root file system.
Prerequisites
Zynq 7000 flat design(xsa) with PL IPs in bitstream
Build Steps
Follow the steps to build and pack the full bitstream and its corresponding dtbo:
- Source the PetaLinux
tool
source /opt/petalinux/petalinux-v<petalinux-version>-final/settings.sh
- Create a Zynq
template project or bsp
project
petalinux-create project -n zynq --template zynq petalinux-create project -s <bsp path> -n zynq
- Go to the
project
cd zynq
- Configure the project with flat xsa if you create a project in template
flow
petalinux-config --get-hw-description <flat.xsa>
- In the petalinux-config command, select FPGA Manager → [*] Fpga
Manager.Note: The PetaLinux FPGA manager configuration performs the following:
- fpga-overlay Machine features
- Enables the required kernel configs to load the fpgamanager driver
- Use the
petalinux-create
command to extract the full bitstream and its corresponding pl dtbo into the PetaLinux rootfs.petalinux-create apps --template dfx_dtg_zynq_full -n can-interface --srcuri "<path-to-xsa>/system.xsa" --enable
Note: If you do not specify--enable
the dtbo and its bitstream is generated in <project>/build/tmp/deploy directory. - To build as part of rootfs you can use the following
commands:
petalinux-build petalinux-build -c rootfs
To build only the application:
petalinux-build -c
Boot Steps
Once the base target is up, run the following command:
fpgautil o /lib/firmware/can interface/pl.dtbo b /lib/firmware/xilinx/can interface/design_1_wrapper.bit.bin