Versal (Segmented Configuration Flow) - 2024.2 English

Versal (Segmented Configuration Flow) - 2024.2 English - UG1144

PetaLinux Tools Documentation: Reference Guide (UG1144)

Document ID

UG1144

Release Date

2024-11-13

Version

2024.2 English

Segmented Configuration flow is quickly booted on an operating system prior to PL loading; NoC + DDR is required in the first programming image. Defer PL loading indefinitely, with the ability to load PL PDI from any primary or secondary boot interface

Prerequisites

Note: The Vivado design should enable segmented configuration parameters when generating the XSA. For more information, see Vivado Segmented Design Flow section.

For SDT flow generate sdt artifacts using xsa, steps for the same mentioned in system-device-tree readme https://github.com/Xilinx/system-device-tree-xlnx.

Versal fixed design(xsa) contains boot pdi which includes Versal cips + NOC + DDR, and pld pdi, which has PL IPs.

SDT Build flow Steps

This section helps to build and boot segmented configuration design flow for Versal platforms.

Source the PetaLinux tool

source /opt/petalinux/petalinux-v<petalinux-version>-final/settings.sh

Create a Versal template project or BSP project

petalinux-create project -n versal-seg-flow --template versal
petalinux-create project -s <bsp path> -n versal-seg-flow

Go to the project
```
cd versal-seg-flow
```
Configure the project with flat xsa if you create project in template flow
```
 petalinux-config --get-hw-description <sdt output path>
```
Enable FPGA manager, select FPGA Manager → [*] Fpga Manager.
Note: The PetaLinux FPGA manager configuration performs the following:
- fpga-overlay Machine features
- Enables the required kernel configs to load the fpgamanager driver
Create the pl application to pack the pl pdi and the pl ips dtbo into rootfs command:
```
petalinux-create apps --template dfx_user_dts -n pl-app --enable --srcuri "<project>/components/plnx_workspace/device-tree/pl-overlay-full/pl.dtsi <project>/project-spec/hw-description/*_pld.pdi"
```
The previous command generates and packages the pl dtbo, pl pdi files into the rootfs(/lib/firmware/xilinx/<pl-app>)
To build the application, use the following command. The following command generates the rootfs containing the rprm, dtbo, and respective pdi files:
```
petalinux-build
petalinux-build -c rootfs
```
To build only the application:
```
petalinux-build -c <pl-app>
```

To boot target with PS generate the boot.bin using the following command:

petalinux-package boot --u-boot (It will pick *_boot.pdi) and packs as part of the boot.bin

XSCT Build flow Steps

This section helps to build and boot segmented configuration design flow for Versal platforms.

Source the PetaLinux tool

source /opt/petalinux/petalinux-v<petalinux-version>-final/settings.sh

Create a Versal template project or BSP project

petalinux-create project -n versal-seg-flow --template versal
petalinux-create project -s <bsp path> -n versal-seg-flow

Go to the project
```
cd versal-seg-flow
```
Configure the project with flat xsa if you create project in template flow
```
 petalinux-config --get-hw-description <fixed.xsa>
```
Enable FPGA manager, select FPGA Manager → [*] Fpga Manager.
Note: The PetaLinux FPGA manager configuration performs the following:
- fpga-overlay Machine features
- Enables the required kernel configs to load the fpgamanager driver
Create the pl application to pack the pl pdi and the pl ips dtbo into rootfs command:
```
petalinux-create apps --template dfx_dtg_versal_full -n pl-app --
 enable --srcuri "<fixed.xsa>"
```
The previous command generates and packages the pl dtbo, pl pdi files into the rootfs(/lib/firmware/xilinx/<pl-app>)
To build the application, use the following command. The following command generates the rootfs containing the rprm, dtbo, and respective pdi files:
```
petalinux-build
petalinux-build -c rootfs
```
To build only the application:
```
petalinux-build -c <pl-app>
```

To boot target with PS generate the boot.bin using the following command:

petalinux-package boot --u-boot (It will pick *_boot.pdi) and packs as part of the boot.bin

Boot Steps

Once the base target is up, run the following command:

fpgautil -o /lib/firmware/can interface/pl.dtbo -b /lib/firmware/xilinx/pl-app/hw_description_pld.pdi