Memory Overview for APU and RPU Executables - 2025.1 English

Memory Overview for APU and RPU Executables - 2025.1 English - UG1137

Zynq UltraScale+ MPSoC Software Developer Guide (UG1137)

Document ID

UG1137

Release Date

2025-06-25

Version

2025.1 English

The following tables give the configurable memory regions for APUs and RPUs.

Note:

In RPU lock-step mode (Lock-Step Operation), R5_0_ATCM_MEM_0 and R5_0_BTCM_MEM_0 memory address are mapped to R5_0_ATCM_LSTEP and R5_0_BTCM_LSTEP memory ranges respectively in the system address map.
In RPU split mode, R5_x_ATCM_MEM_0, and R5_x_BTCM_MEM_0 memory address are mapped to R5_x_ATCM_SPLIT and R5_x_BTCM_SPLIT memory ranges respectively in the system address map.
QSPI memory is accessible when QSPI controller is in linear mode.

See the System Addresses chapter of the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for more information.

See Real-time Processing Unit (RPU) and On-Chip Memory (OCM) sections of the Zynq UltraScale+ Device Technical Reference Manual (UG1085) for more information on RPU, R5, and OCM.

Table 1. Configurable Memory Regions for APUs
Memory Type	Start Address	Size
DDR Low	0x00000000	2 GB
DDR High	0x800000000	2 GB
OCM	0xFFFC0000	256 KB
QSPI	0xC0000000	512 MB

Table 2. Configurable Memory Regions for RPU Lock-Step Mode
Memory Type	Start Address	Size
DDR Low	0x100000	2047 MB
OCM	0xFFFC0000	256 KB
QSPI	0xC0000000	512 MB
R5_0_ATCM_MEM_0	0x00000	64 KB
R5_0_BTCM_MEM_0	0x20000	64 KB
R5_TCM_RAM_0_MEM	0x00000	256 KB

Table 3. Configurable Memory Regions for RPU Split Mode
Memory Type	Start Address	Size
R5_0
DDR Low	0x100000	2047 MB
OCM	0xFFFC0000	256 KB
QSPI	0xC0000000	512 MB
R5_0_ATCM_MEM_0	0x00000	64 KB
R5_0_BTCM_MEM_0	0x20000	64 KB
R5_1
DDR Low	0x100000	2047 MB
OCM	0xFFFC0000	256 KB
QSPI	0xC0000000	512 MB
R5_1_ATCM_MEM_0	0x00000	64 KB
R5_1_BTCM_MEM_0	0x20000	64 KB

Note: BootROM always copies First Stage Boot Loader (FSBL) from 0xFFFC0000 and it is not configurable. If FSBL is compiled for a different load address, Bootgen can refuse it as CSU BootROM (CBR) does not parse partition headers in the boot image but merely copies the FSBL code at a fixed OCM memory location (0xfffc0000). See System Boot and Configuration for more information on Bootgen.