Introduction - Introduction - 2026.1 English

Introduction - Introduction - 2026.1 English - UG1118

Vivado Design Suite User Guide: Creating and Packaging Custom IP (UG1118)

Document ID

UG1118

Release Date

2026-07-23

Version

2026.1 English

Important: Some AMD IP requires licensing. After purchasing the required license, you can include AMD IP in your design.

The AMD Vivado™ Integrated Design Environment (IDE) Create and Package New IP wizard lets you create and package the following:

IP using source files and information from a Vivado Design Suite project
BD, XCI, and XCIX files
IP from a specified directory
A template for AXI4 peripherals that includes:
- HDL files
- Drivers
- A test application
- An example template
- Verification IP: See the following documents for more information:
  - AXI Verification IP LogiCORE IP Product Guide (PG267)
  - AXI4-Stream Verification IP LogiCORE IP Product Guide (PG277)
  - Zynq UltraScale+ MPSoC Verification IP Data Sheet (DS940)
  - Zynq 7000 SoC Verification IP Data Sheet (DS941)
Video: Vivado QuickTake Video: How to Use AXI Verification IP to Verify/Debug Using Simulation

The Create and Package New IP wizard can generate AMD-supported AXI interfaces. These are:

AXI4: For memory-mapped interfaces, which allows burst of up to 256 data transfer cycles with a single address phase.
AXI4-Lite: A light-weight, single transaction memory-mapped interface.
AXI4-Stream: For high-speed streaming data.

For more information on the AMD adoption of AXI, see the Vivado Design Suite: AXI Reference Guide (UG1037).

Note: For the simple purpose of adding custom RTL for use in IP integrator, the Module Reference feature is available and described in the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).