The primary file types and their associated standard file groups include:
HDL Source Files (.v, .vhdl, .sv): These are the main design files and are typically placed in the Synthesis and Simulation file groups. They form the core logic of the IP.
- Constraint Files (.xdc)
- These files contain design constraints.
- Implementation (XDC)
- Typically contains constraints for post-synthesis implementation (for example, pin locations), which are processed when the IP is used in a top-level design.
- Out-Of-Context (OOC) (XDC)
- Contains constraints like clock definitions needed for the IP's standalone synthesis run, which is used to create a design checkpoint (DCP).
- Test Bench Files (.v, .vhdl, .sv)
- Files for verification purposes are placed in the Test Bench file group, which can be further specified as Verilog or VHDL Test Bench.
- Documentation Files (.pdf, .gif, .jpeg, .png)
- Data Sheet/Getting Started Guide: These use standard document formats like PDF.
- Icons
- Used for the IP catalog or customization GUI, these files are typically GIF, JPEG, or PNG images.
- Software Driver Files
- Files for any associated software (for example, C/C++ source code) are placed in the Software Drivers group.
- Tcl Scripts (.tcl)
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Used for various purposes, such as controlling the custom GUI layout (Custom UI Layout) or creating example projects (Examples Script).
Managing File Types
Vivado attempts to automatically categorize files, but you can adjust this on the File Groups page in the "Package IP" window.
Navigate to the File Groups section in the Package IP window. The files are listed under their assigned groups. You can expand the groups to see individual files. To adjust a file's group, you can typically right-click and modify its properties or use the "Merge changes from File Groups Wizard" link if you've added new files to your project.
Ensure that files associated with the IP are located within the IP's root directory for proper packaging and reuse.