Layer Count Optimization

Recommended Design Rules and Strategies for BGA Devices User Guide (UG1099)

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Versal® architecture, UltraScale™ architecture, 7 series, and 6 series packages have full matrices of solder balls. The true number of layers required for effective routing of these packages is dictated by a variety of factors, including:
  • BGA Size (quantity of pins)
  • Pad size, pad pitch, and trace width
  • Fixed pinouts
  • Back Drilling
  • Fabrication Technologies

BGA Size

The quantity of pins in a BGA indicates the number of signals to route. Because of physical space constraints, the quantity of signals required to route is proportional to the amount of signal layers required.

Pad Size, Pad Pitch, and Trace Width

The pad size and pitch determine the available space between adjacent balls for signal escape. Based on the chosen trace width, one or two signals can be routed between adjacent pads. If one signal escapes between adjacent pads, then one signal row can be routed on a single metal layer. The exception to this is the outermost row, which allows two routes per layer.

To facilitate routing in the ball grid area, necking down the trace width in the critical space between the BGA pads/vias (the breakout area) is allowable. This then allows for two signal rows to be routed on a single metal layer (or three if routing the outermost row). The traces can then be widened after they escape the breakout area. Changes in width over very short distances can cause small impedance changes. Validate these issues with the board vendor and signal integrity engineers responsible for the design.

Fixed Pinouts

Xilinx FPGA and ACAP pinouts are designed with maximum flexibility in mind. However, certain FPGA/ACAP signals, such as JTAG, transceiver inputs and outputs, and memory controller signals (among others) have fixed locations, which means routing of these signals is limited compared to other signals that can be swapped as needed. Fixed locations lead to layout trade-offs that can have an impact on the number of required signal layers.

Back Drilling

Back drilling is the technique is which unused via stubs have their metal drilled away to remove the potential for the stubs to cause reflections which can cause signal integrity problems. Typically, back drilling can prevent the ability to route more than one signal in-between pads and vias due to manufacturability concerns. Always consult with the PCB manufacturer regarding the ability to back drill before beginning and layout activity.