Layer Count Estimation and Optimization - Layer Count Estimation and Optimization - UG1099

Layer Count Estimation

A quick way to estimate the number of signal routing layers required to fully break out signal pins from the FPGA would be to use the following equation:

Figure 1. Layers

For AMD FPGAs, MPSoCs/RFSoCs, and adaptive SoCs, the quantity of signals is approximately 60% of the number of BGA balls. The other 40% are power and ground signals that are most often routed directly down to their own dedicated planes by vias. The equation assumes full I/O utilization. If fewer I/Os are used, the number of signals to route goes down accordingly.

Routing channels are the number of available routing paths out of the BGA area (the number of BGA pins on one side minus one, times four sides). The following figure shows a 5x5 grid with sixteen total routing channels (four routing channels per side times four sides).

Figure 2. Definition of Routing Channel (16 Total Routing Channels Shown)