PS Power Up Behavior - UG1091

Kria SOM Carrier Card Design Guide (UG1091)
Document ID
UG1091
Release Date
2025-09-18
Revision
1.6 English
Figure 1. PS Power Up Sequence Diagram

  1. Carrier-provided SOM5V0 is initialized and stabilized.
  2. Carrier deasserts PWROFF_C2M_L (t0).
  3. SOM PS core and I/O power initialized in the correct sequence (parallel to PL sequence).
  4. SOM PS power is stabilized.
    1. Sequencer asserts VCCOEN_PS_M2C (t1).
    2. PS power stabilization occurs within 50 ms.
    3. Carrier enables all supplies related to PS MIO peripherals.
      Note: VCCOEN_PS_M2C is required to be asserted by the power sequencer prior to allowing the power-on sequence to continue, that is the release of PS_POR_L.
  5. SOM full-power domain (FPD) and low-power domain (LPD) sequencing is initialized.
  6. SOM FPD and LPD power is stabilized.
    1. Sequencer asserts PWRGD_FPD_M2C and PWRGD_LPD_M2C (t2).
    2. PWRGD_FPD_M2C and PWRGD_LPD_M2C are tied together on the K26 SOM.
    3. Asserts 50 ms after PWROFF_C2M_L is deasserted.
  7. SOM releases PS reset.
    1. Sequencer releases PS_POR_L1 (t3).
    2. This occurs 10 ms after PWRGD_FPD_M2C and PWRGD_LPD_M2C asserts.
    3. Carrier can now control the SOM power on reset (POR_B) signaling to hold off boot for carrier related delays, or coordination.
  8. Carrier assertion of PS_POR_L starts a hardware reset of the MPSoC. This leaves the power supplies fully sequenced and available for immediate use by the SOM upon PS_POR_L release, without needing to sequence the MPSoC a second time.