PL Power Up Behavior - UG1091

Kria SOM Carrier Card Design Guide (UG1091)
Document ID
UG1091
Release Date
2025-09-18
Revision
1.6 English
Figure 1. PL Power Up Sequence Diagram

  1. Carrier-provided SOM5V0 is initialized and stabilized
  2. Carrier deasserts PWROFF_C2M_L (t0)
  3. All SOM PL power initialized in the correct sequence. Parallel to PS sequence.
  4. SOM PL core and VCU power stabilized:
    1. Sequencer asserts VCCOEN_PL_M2C (t1)
    2. PL power stabilization occurs within 55 ms
    3. Carrier enables all VCCO supplies related to PL peripherals
  5. All remaining SOM power stabilized:
    1. Sequencer asserts PWRGD_PL_M2C (t2)
    2. Asserts 55 ms after PWROFF_C2M_L deassertion