PL Power Down - UG1091

Kria SOM Carrier Card Design Guide (UG1091)

Document ID
UG1091
Release Date
2025-09-18
Revision
1.6 English
Figure 1. PL Power Down Sequence Diagram

  1. Carrier asserts PWROFF_C2M_L (t0). Power sequencers immediately begin rolling back all power solutions.
  2. Upon first power supply not meeting the required stabilization requirements, all status signals and request signaling from the SOM is deasserted (t1)
  3. At VCCOEN_PL_M2C (t2) deassertion carrier turns off power to the VCCO supplies.
  4. Carrier remove SOM5V0 (t3).
    1. SOM5V0 does not have to be removed. However, the discharge of related power supplies and power up rules must be observed before PWROFF_C2M_L (t5) can be deasserted.
    2. (t4) is observed to be the same point as (t0) in the power up sequence.
  5. Rails discharge for up to 2 seconds (t5).
Important: It is a good design practice to delay the re-release of PWROFF_C2M_L for more than 2 seconds. This is because full discharge of the SOM rails depends on many factors including device temperature, temperature grade, and the performance/power draw of the software and firmware being run on the SOM at the time of PWROFF_C2M_L assertion. Failure to provide enough time for the system to discharge rails can provide a locked state for the power sequencer. Rails powering up under the incorrect order can cause the sequencer to halt power-up sequence for SOM protection. The only resolution to this locked state is a complete power down of all rails, including the main SOM 5.0 V input.