reg_hostcontrol1 (SDIO) Register Description
| Register Name | reg_hostcontrol1 |
|---|---|
| Offset Address | 0x0000000028 |
| Absolute Address |
0x00FF160028 (SD0) 0x00FF170028 (SD1) |
| Width | 8 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Controller Configuration. |
Program DMA modes, LED Control, Data Transfer Width, High Speed Enable, Card detect test level and signal selection
reg_hostcontrol1 (SDIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| hostctrl1_cdsigselect | 7 | rwNormal read/write | 0x0 | This bit selects source for card detection. 0: SD_CDn is selected (for normal use) 1: The card detect test level is selected |
| hostctrl1_cdtestlevel | 6 | rwNormal read/write | 0x0 | This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not. Generates (card ins or card removal) interrupt when the normal int sts enable bit is set. 0 No Card 1 Card Inserted |
| hostctrl1_extdatawidth | 5 | rwNormal read/write | 0x0 | This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the Capabilities register. If a device supports 8-bit bus mode, this bit may be set to 1. If this bit is 0, bus width is controlled by Data Transfer Width in the Host Control 1 register.This bit is not effective when multiple devices are installed on a bus slot (Slot Type is set to 10b in the Capabilities register). In this case, each device bus width is controlled by Bus Width Preset field in the Shared Bus register. 0 Bus width is selected by data transfer width 1 8-bit bus width |
| hostctrl1_dmaselect | 4:3 | rwNormal read/write | 0x0 | One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register. 00 SDMA 01 32 bit ADMA1 address 10 32 bit ADMA2 address 11 64 bit ADMA2 Address Note: Switching between 32-bit and 64-bit operation will require a reset. Write the [swreset_for_cmd] bit of SDHC register reg_software to reset. |
| hostctrl1_highspeedena | 2 | rwNormal read/write | 0x0 | This bit is optional. Before setting this bit, the driver shall check the High Speed Support in the capabilities register. If this bit is set to 0 (default), the HC outputs CMD line and DAT lines at the falling edge of the SD clock (up to 25 MHz/20MHz for MMC). If this bit is set to 1,the HC outputs CMD line and DAT lines at the rising edge of the SD clock (up to 50 MHz for SD/52MHz for MMC)/208Mhz (for SD3.0). If Preset Value Enable in the Host Control 2 register is set to 1, Host Driver needs to reset SD Clock Enable before changing this field to avoid generating clock glitches. After setting this field, the Host Driver sets SD Clock Enable again. 0: Normal Speed Mode. 1: High Speed Mode. |
| hostctrl1_datawidth | 1 | rwNormal read/write | 0x0 | Select the data width of the controller. The driver shall select it to match the data width of the SD card. 0: 1-bit mode 1: 4-bit mode |
| hostctrl1_ledcontrol | 0 | rwNormal read/write | 0x0 | This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands, this bit can be set during all transactions. It is not necessary to change for each transaction. 0 LED Off 1 LED On |