reg_ctrl (USB3_REGS) Register Description
| Register Name | reg_ctrl |
|---|---|
| Offset Address | 0x0000000060 |
| Absolute Address |
0x00FF9D0060 (USB3_0) 0x00FF9E0060 (USB3_1) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | reg_ctrl |
reg_ctrl (USB3_REGS) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | razRead as zero | 0x0 | reserved for future |
| slverr_enable | 0 | rwNormal read/write | 0x0 | By default, invalid address requests are ignored. However, a maskable interrupt exsists. By enabling this slverr_enable invalid address requests cause a slverr to occur. Enable/Disable SLVERR during address decode failure. 0: SLVERR is disabled. For request address: Writes are ignored. Read returns 0. 1: SLVERR is enabled. For requestes address, SLVERR is asserted. Writes are ignored. Read returns 0. |