| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:27 | razRead as zero | 0x0 | reserved |
| Reserved | 26:18 | razRead as zero | 0x0 | reserved |
| CLKOUTDIV | 17:16 | rwNormal read/write | 0x1 | This does not change the VCO frequency, just the output frequency |
| Reserved | 15 | razRead as zero | 0x0 | reserved |
| FBDIV | 14:8 | rwNormal read/write | 0x51 | The integer portion of the feedback divider to the PLL |
| Reserved | 7:4 | razRead as zero | 0x0 | reserved |
| BYPASS | 3 | rwNormal read/write | 0x1 | Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) |
| pctrl_por_in | 2 | rwNormal read/write | 0x1 | Drives pctrl_por_b_in pin of PLL. An invertor is there before PLL on this bit. 1will keep in reset mode. |
| pss_pwr_por | 1 | rwNormal read/write | 0x1 | Drives pss_pwr_por_b pin of PLL. An invertor is there before PLL on this bit.1will keep in reset mode. |
| RESET | 0 | rwNormal read/write | 0x1 | Asserts Reset to the PLL. 1will keep PLL in reset mode. |