Timing_Register (NAND) Register Description
| Register Name | Timing_Register |
|---|---|
| Offset Address | 0x000000002C |
| Absolute Address | 0x00FF10002C (NAND) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interface Timing Control. |
Timing_Register (NAND) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:19 | razRead as zero | 0x0 | reserved |
| dqs_buff_sel_out | 18:15 | rwNormal read/write | 0x0 | For write transaction program this value based on tDS value. Write data transaction values NVDDR Mode 0 - 4'h6 NVDDR Mode 1 - 4'h5 NVDDR Mode 2 - 4'h4 NVDDR Mode 3 - 4'h3 NVDDR Mode 4 - 4'h2 NVDDR Mode 5 - 4'h2 Note: Change this value only when controller is not communicating with the memory device. |
| tadl_time | 14:7 | rwNormal read/write | 0x0 | Address Latch Enable to Data Loading time. During write if pgm_pg_reg_clr bit is set then this value must be programmed. Note: Change this value only when controller is not communicating with the memory device. |
| dqs_buff_sel_in | 6:3 | rwNormal read/write | 0x0 | For read transaction program this value based on tDQSQ value. Read data transaction values NVDDR Mode 0 - 4'h6 NVDDR Mode 1 - 4'h5 NVDDR Mode 2 - 4'h4 NVDDR Mode 3 - 4'h3 NVDDR Mode 4 - 4'h2 NVDDR Mode 5 - 4'h2 Note: Change this value only when controller is not communicating with the memory device. |
| slow_fast_tcad | 2 | rwNormal read/write | 0x0 | 0: slow device (tCADs). 1: fast device (tCADf). Note: Change this value only when controller is not communicating with the memory device. |
| tccs_time | 1:0 | rwNormal read/write | 0x0 | Change column setup time. 00: 500ns 01: 100ns 10: 200ns 11: 300ns Note: Change this value only when controller is not communicating with the memory device. |