SMMU_SIDR1 (SMMU500) Register - SMMU_SIDR1 (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

SMMU_SIDR1 (SMMU500) Register Description

Register NameSMMU_SIDR1
Offset Address0x0000000024
Absolute Address 0x00FD800024 (SMMU_GPV)
Width32
TyperoRead-only
Reset Value0x30000F10
DescriptionProvides SMMU capability information.

SMMU_SIDR1 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PAGESIZE31roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NUMPAGENDXB30:28roRead-only0x3Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NUMS2CB23:16roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SMCD15roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SSDTP12roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NUMSSDNDXB11:8roRead-only0xFRefer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NUMCB 7:0roRead-only0x10Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details