SMMU_SGFSYNR0 (SMMU500) Register - SMMU_SGFSYNR0 (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

SMMU_SGFSYNR0 (SMMU500) Register Description

Register NameSMMU_SGFSYNR0
Offset Address0x0000000050
Absolute Address 0x00FD800050 (SMMU_GPV)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionContains fault syndrome information relating to SMMU_sGFSR.

SMMU_SGFSYNR0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ATS 6roRead-only0x0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSATTR 5rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSSTATE 4rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IND 3rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PNU 2rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
WNR 1rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details