SMMU_CB1_PRRR_MAIR0 (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

SMMU_CB1_PRRR_MAIR0 (SMMU500) Register Description

Register NameSMMU_CB1_PRRR_MAIR0
Offset Address0x0000011038
Absolute Address 0x00FD811038 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPrimary region remap register if AArch32 short descriptor scheme is selected. Controls top-level mapping of the TEX, C, and B memory region attributes. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.

SMMU_CB1_PRRR_MAIR0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
NOS731rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS630rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS529rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS428rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS327rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS226rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS125rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NOS024rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NS119rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NS018rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
DS117rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
DS016rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR715:14rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR613:12rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR511:10rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR4 9:8rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR3 7:6rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR2 5:4rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR1 3:2rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
TR0 1:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details