SMMU_CB11_PMEVTYPER0 (SMMU500) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

SMMU_CB11_PMEVTYPER0 (SMMU500) Register Description

Register NameSMMU_CB11_PMEVTYPER0
Offset Address0x000001BE80
Absolute Address 0x00FD81BE80 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionProvides event type resources in the register map of a translation context bank. Controls which events are counted by the corresponding event counter

SMMU_CB11_PMEVTYPER0 (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
P31rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
U30rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSP29rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSU28rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
EVENT 4:0rwNormal read/write0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details