RST_FPD_APU (CRF_APB) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

RST_FPD_APU (CRF_APB) Register Description

Register NameRST_FPD_APU
Offset Address0x0000000104
Absolute Address 0x00FD1A0104 (CRF_APB)
Width24
TyperwNormal read/write
Reset Value0x00003D0F
DescriptionSoftware Controlled APU MPCore Resets.

RST_FPD_APU (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
acpu3_pwron_reset13rwNormal read/write0x1APU core3 POR reset.
acpu2_pwron_reset12rwNormal read/write0x1APU core2 POR reset.
acpu1_pwron_reset11rwNormal read/write0x1APU core1 POR reset.
acpu0_pwron_reset10rwNormal read/write0x1APU core0 POR reset.
Reserved 9rwNormal read/write0x0reserved
apu_l2_reset 8rwNormal read/write0x1L2 Cache reset.
acpu3_reset 3rwNormal read/write0x1APU core3 system reset.
acpu2_reset 2rwNormal read/write0x1APU core2 system reset.
acpu1_reset 1rwNormal read/write0x1APU core1 system reset.
acpu0_reset 0rwNormal read/write0x1APU core0 system reset.