| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:6 | razRead as zero | 0x0 | Reserved for future use |
| nVALRESET | 5 | roRead-only | 0x1 | Validation Signal: Request for a reset |
| nVALIRQ | 4 | roRead-only | 0x1 | Validation Signal: Request for an interrupt |
| nVALFIQ | 3 | roRead-only | 0x1 | Validation Signal: Request for an fast interrupt |
| nWFIPIPESTOPPED | 2 | roRead-only | 0x1 | When LOW, this indicates the CPU is in standby mode because of a WFI instruction. The
CPU pipeline is inactive |
| nWFEPIPESTOPPED | 1 | roRead-only | 0x1 | When LOW, this indicates that the CPU is in standby mode because of a WFE instruction.The CPU pipeline is inactive |
| nCLKSTOPPED | 0 | roRead-only | 0x1 | When LOW, this indicates clock has been stopped because processor is in Standby Mode.It is never asserted without one of WFIPIPESTOPPEDm or WFEPIPESTOPPEDm. |