R00_END (XMPU_DDR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

R00_END (XMPU_DDR) Register Description

Register NameR00_END
Offset Address0x0000000104
Absolute Address 0x00FD000104 (DDR_XMPU0_CFG)
0x00FD010104 (DDR_XMPU1_CFG)
0x00FD020104 (DDR_XMPU2_CFG)
0x00FD030104 (DDR_XMPU3_CFG)
0x00FD040104 (DDR_XMPU4_CFG)
0x00FD050104 (DDR_XMPU5_CFG)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegion 0 End Address

Each region is defined by a start and end address base addresses that represent a 1MB page size.

R00_END (XMPU_DDR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:28roRead-only0x0reserved
ADDR27:0rwNormal read/write0x0Bits [27:8] correspond to address bits [39:20].
Bits [7:0] are reserved.