QOS_IRQ_ENABLE (DDR_QOS_CTRL) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

QOS_IRQ_ENABLE (DDR_QOS_CTRL) Register Description

Register NameQOS_IRQ_ENABLE
Offset Address0x0000000208
Absolute Address 0x00FD090208 (DDR_QOS_CTRL)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)

QOS_IRQ_ENABLE (DDR_QOS_CTRL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:11razRead as zero0x0Reserved for future use
DDRC_WR_POISON10woWrite-only0x0See QOS_IRQ_STATUS register for details
DDRC_RD_POISON 9woWrite-only0x0See QOS_IRQ_STATUS register for details
MRR_DATA_VALID 8woWrite-only0x0See QOS_IRQ_STATUS register for details
PC_COPY_DONE 7woWrite-only0x0See QOS_IRQ_STATUS register for details
DFI_ALT_ERR 6woWrite-only0x0See QOS_IRQ_STATUS register for details
DFI_ALT_ERR_MAX 5woWrite-only0x0See QOS_IRQ_STATUS register for details
DFI_ALT_ERR_FTL 4woWrite-only0x0See QOS_IRQ_STATUS register for details
DFI_INIT_COMP 3woWrite-only0x0See QOS_IRQ_STATUS register for details
DDRECC_UNCRERR 2woWrite-only0x0See QOS_IRQ_STATUS register for details
DDRECC_CORERR 1woWrite-only0x0See QOS_IRQ_STATUS register for details
INV_APB 0woWrite-only0x0See QOS_IRQ_STATUS register for details