PWRSTAT (APU) Register Description
| Register Name | PWRSTAT |
|---|---|
| Offset Address | 0x0000000094 |
| Absolute Address | 0x00FD5C0094 (APU) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Power Status Register |
PWRSTAT (APU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CLREXMONACK | 17 | roRead-only | 0x0 | Acknowledge the receipt of CLREXMONREQ; the processor EVENT registers have been set HIGH. |
| L2FLUSHDONE | 16 | roRead-only | 0x0 | L2 hardware flush is done |
| DBGNOPWRDWN | 3:0 | roRead-only | 0x0 | Indicate that power must not be removed from CPUn island |