PP1_WB2_MRT_OFFSET (GPU) Register Description
| Register Name | PP1_WB2_MRT_OFFSET |
|---|---|
| Offset Address | 0x000000A320 |
| Absolute Address | 0x00FD4BA320 (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | WB2 MRT Offset Register |
PP1_WB2_MRT_OFFSET (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| WB2_MRT_OFFSET | 31:3 | rwNormal read/write | 0x0 | Offset value giving the distance in memory between each MRT |
| _ | 2:0 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |