PP1_MMU_INT_MASK (GPU) Register Description
| Register Name | PP1_MMU_INT_MASK |
|---|---|
| Offset Address | 0x000000501C |
| Absolute Address | 0x00FD4B501C (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | MMU Interrupt Mask Register |
PP1_MMU_INT_MASK (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:2 | rwNormal read/write | 0x0 | Reserved, read undefined, write as zero |
| read_bus_error | 1 | rwNormal read/write | 0x0 | Read bus error |
| page_fault | 0 | rwNormal read/write | 0x0 | Page fault |