PP1_MMU_COMMAND (GPU) Register Description
| Register Name | PP1_MMU_COMMAND |
|---|---|
| Offset Address | 0x0000005008 |
| Absolute Address | 0x00FD4B5008 (GPU) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | MMU Command Register |
PP1_MMU_COMMAND (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:3 | woWrite-only | 0x0 | Reserved, read undefined, write as zero |
| MMU_CMD | 2:0 | woWrite-only | 0x0 | MMU_CMD. This can be: 000:MMU_ENABLE_PAGING. Enable paging. 001:MMU_DISABLE_PAGING. Disable paging. 010:MMU_ENABLE_STALL. Turn on stall mode. 011:MMU_DISABLE_STALL. Turn off stall mode. 100:MMU_ZAP_CACHE. Zap the entire page table cache. 101:MMU_PAGE_FAULT_DONE. Leave page fault mode. 110:MMU_FORCE_RESET. Reset the MMU. |