PP0_WRITE_BOUNDARY_ENABLE (GPU) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PP0_WRITE_BOUNDARY_ENABLE (GPU) Register Description

Register NamePP0_WRITE_BOUNDARY_ENABLE
Offset Address0x0000009040
Absolute Address 0x00FD4B9040 (GPU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionWrite Boundary Enable Register

PP0_WRITE_BOUNDARY_ENABLE (GPU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1rwNormal read/write0x0Reserved, write as zero, read undefined.
_ 0rwNormal read/write0x0When set to 1, the renderer is not able to write to addresses outside the
boundaries set by the WRITE_BOUNDARY_LOW and
WRITE_BOUNDARY_HIGH bus address values.