PP0_STENCIL_CLEAR_VALUE (GPU) Register Description
| Register Name | PP0_STENCIL_CLEAR_VALUE |
|---|---|
| Offset Address | 0x0000008014 |
| Absolute Address | 0x00FD4B8014 (GPU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Stencil Clear Value Register |
PP0_STENCIL_CLEAR_VALUE (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | rwNormal read/write | 0x0 | Reserved, write as zero, read undefined. |
| STENCIL_CLEAR_VALUE | 7:0 | rwNormal read/write | 0x0 | The 8-bit stencil value of the stencil tile buffer is logically cleared whenever processing of a new tile starts. If you do not want the stencil tile buffer to be cleared, the content of the stencil tile buffer can be pre-loaded by using a textured quad and stencil replacement technique. For more information see the explanation of subword 3 in Render state word data structures on page 3-132. See also Table 3-231 on page 3-181 and the corresponding description of texel format value 50. |