PIDR5 (A53_PMU_2) Register Description
| Register Name | PIDR5 |
|---|---|
| Offset Address | 0x0000000FD4 |
| Absolute Address | 0x00FEE30FD4 (CORESIGHT_A53_PMU_2) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Performance Monitors Peripheral Identification Register 4 |
PIDR5 (A53_PMU_2) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:0 | roRead-only | 0x0 | reserved |