| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:11 | razRead as zero | 0x0 | Status for an address decode error interrupt. |
| UE_RMW | 10 | woWrite-only | 0x0 | see OCM_INT_STATUS register for details |
| FIX_BURST_WR | 9 | woWrite-only | 0x0 | see OCM_INT_STATUS register for details |
| FIX_BURST_RD | 8 | woWrite-only | 0x0 | see OCM_INT_STATUS register for details |
| ECC_UE | 7 | woWrite-only | 0x0 | see OCM_INT_STATUS register for details |
| ECC_CE | 6 | woWrite-only | 0x0 | see OCM_INT_STATUS register for details |
| LOCK_ERR_WR | 5 | woWrite-only | 0x0 | see OCM_INT_STATUS register for details |
| LOCK_ERR_RD | 4 | woWrite-only | 0x0 | see OCM_INT_STATUS register for details |
| INV_OCM_WR | 3 | woWrite-only | 0x0 | see OCM_INT_STATUS register for details |
| INV_OCM_RD | 2 | woWrite-only | 0x0 | see OCM_INT_STATUS register for details |
| PWR_DWN | 1 | woWrite-only | 0x0 | see OCM_INT_STATUS register for details |
| INV_APB | 0 | woWrite-only | 0x0 | see OCM_INT_STATUS register for details |