OCM_ECC_CTRL (OCM) Register Description
| Register Name | OCM_ECC_CTRL |
|---|---|
| Offset Address | 0x0000000014 |
| Absolute Address | 0x00FF960014 (OCM) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | control register for OCM |
OCM_ECC_CTRL (OCM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:3 | razRead as zero | 0x0 | Reseved for future use |
| FI_MODE | 2 | rwNormal read/write | 0x0 | User can inject error in OCM DATA & Syndrome bits by writing fault inject register along with fault inject counter register. OCM loads the internal counter with the fault inject counter regiser value and count down on every clock cycle. Once counter reaches to "zero", ocm injects one/mutiple error indicated by fault inject register depending on FI_MODE 0 = Inject single error on write trasaction after FI Counter reaches to zero 1= Inject error on every write transaction after FI counter reaches to zero |
| DET_ONLY | 1 | rwNormal read/write | 0x0 | 0 = ECC corrects single bit error 1 = ECC does not correct single bit error (detect only) , double bit errors are detected in both case |
| ECC_ON_OFF | 0 | rwNormal read/write | 0x0 | ON/OFF controll of ECC port 1 = on ; 0 = OFF. This bit should be initialized during system boot. It should not be changed while OCM is in use |