OCFG (USB3_XHCI) Register Description
| Register Name | OCFG |
|---|---|
| Offset Address | 0x000000CC00 |
| Absolute Address |
0x00FE20CC00 (USB3_0_XHCI) 0x00FE30CC00 (USB3_1_XHCI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | OTG Configuration Register This register specifies the HNP and SRP capability of the controller |
OCFG (USB3_XHCI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:6 | roRead-only | 0x0 | Reserved |
| DisPrtPwrCutoff | 5 | rwNormal read/write | 0 | OTG Disable Port Power Cut Off (DisPrtPwrCutoff) - 0: The core automatically turns off the VBUS by clearing the OCTL.PrtPwrCtl after A_WAIT_BCON Timeout whenever the port is disconnected in disconnected state. If Hibernation is enabled and when a hibernation request is received in disconnected state, the core switches off VBUS instantly by clearing the OCTL.PrtPwrCtl. - 1: The core maintains VBUS ON even after A_WAIT_BCON Timeout when port is in disconnected state. The core is in a A_WAIT_BCON state continuously waiting for a Connect. If hibernation is enabled and when hibernation request is received in disconnected state, the core maintains VBUS ON and continues to drive VBUS even in hibernation. |
| OTGHibDisMask | 4 | rwNormal read/write | 0 | OTG Hibernation Disable Mask. - 0 - Any change in PHY input signals relevant to OTG (ID, Vbus-valid, B-Valid) are masked from generating a corresponding event when the core receives Hibernation Save request from Host or Device Driver. The change in signals is masked until the Host or Device Run/Stop is programmed to 1. - 1 - The PHY input signals are not masked even after the core receives the Hibernation Save request from Host or Device Driver. For normal functionality, this bit must be 1b0. |
| OTGSftRstMsk | 3 | rwNormal read/write | 0 | OTG Soft Reset Mask. This bit is used to mask specific soft resets from affecting the OTG functionality of the core. When set, the xHCI-based USBCMD.HCRST in host mode and DCTL.CSftRst in device mode is masked from affecting reset signal outputs sent to the PHY, the OTG FSM logic of the core and also the resets to the VBUS filters inside the core. - 1b0: The xHCI-based USBCMD.HCRST and DCTL.CSftRst resets the OTG logic of the core. - 1b1: The xHCI-based USBCMD.HCRST and DCTL.CSftRst is masked from the OTG logic of the core. This bit can be programmed to allow existing xHCI flows (with USBCMD.HCRST programming) to function in OTG scenarios without any software changes. This bit must be programmed only when GCTL.PrtCapDir = 2b11. Otherwise it must be set at 1b0. Note: When using the core for OTG2 or OTG3 applications, it is not recommended to program USBCMD.HCRST during role switch. |
| OTG_Version | 2 | rwNormal read/write | 0 | This is a debug bit and it must always be set to 1b0. |
| HNPCap | 1 | rwNormal read/write | 0 | RSP/HNP Capability. The terminology RSP is used when the core is operating in SS mode, and HNP is used when the core is operating in non-SS mode. The application uses this bit to control the RSP/HNP capabilities. - 1b0: RSP/HNP capability is not enabled. - 1b1: RSP/HNP capability is enabled. |
| SRPCap | 0 | rwNormal read/write | 0 | SRP Capability. The application uses this bit to control the SRP capabilities. - 1b0: SRP capability is not enabled. - 1b1: SRP capability is enabled. If this bit is not set for B-device, it cannot request the connected A-device (host) to activate Vbus and start a session. If this bit is not set for A-device, it cannot detect the SRP from B-device (device) to activate Vbus and start a session. |