Match_1_Counter_2 (TTC) Register Description
| Register Name | Match_1_Counter_2 |
|---|---|
| Offset Address | 0x0000000034 |
| Absolute Address |
0x00FF110034 (TTC0) 0x00FF120034 (TTC1) 0x00FF130034 (TTC2) 0x00FF140034 (TTC3) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Match value |
Match_1_Counter_2 (TTC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Match | 31:0 | rwNormal read/write | 0x0 | When a counter has the same value as is stored in one of its match registers and match mode is enabled, a match interrupt is generated. Each counter has three match registers. |