MB_FAULT_STATUS (PMU_GLOBAL) Register Description
| Register Name | MB_FAULT_STATUS |
|---|---|
| Offset Address | 0x000000052C |
| Absolute Address | 0x00FFD8052C (PMU_GLOBAL) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | PMU Fault Status; Lockstep, Fatal, Selfcheck, Sleep Instruction. |
The faults are handled by the PMU ROM code. But this register is also useful for debugging. Primary (nominal) Fault Detection: The primary detector compares the outputs from the PMU. The status is held in the lower 16 bits of this register. Secondary (redundant) Fault Detection : The secondary detector compares the outputs from the PMU. This is a backup detector in case the operation of the primary detector experiences a fault. The status is held in the upper 16 bits of this register. Read-only. Reset by any PMU reset.
MB_FAULT_STATUS (PMU_GLOBAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| R_FFail | 31:24 | roRead-only | 0x0 | Redundant (secondary) fatal fault detection. First lockstep mismatch. Bit [24] between processor 1 and 2. Bit [25] between processor 1 and 3. Bit [26] between processor 2 and 3. Redundant (secondary) first selfcheck comparator Error. Bit [27] between processor 1 and 2. Bit [28] between processor 1 and 3. Bit [29] between processor 2 and 3. First Selfcheck Voter Error. Bit [30] Selfcheck Voter Error. First Uncorrectable ECC Error. Bit [31] Uncorrectable Error from PMU RAM ECC. |
| Reserved | 23:20 | roRead-only | 0x0 | reserved |
| R_Sleep_Rst | 19 | roRead-only | 0x0 | Redundant (secondary) fault detection. PMU Sleep Instruction Response. 0: causes the PMU CPUs to go to sleep. 1: causes the PMU CPUs to reset. Read-only. |
| R_LSFail | 18:16 | roRead-only | 0x0 | Redundant (secondary) fault detection. Frist lockstep mismatch. Bit [16] processors 1 and 2. Bit [17] processors 1 and 3. Bit [18] processors 2 and 3. |
| N_FFail | 15:8 | roRead-only | 0x0 | Nominal (primary) fatal fault detection. First lockstep mismatch. Bit [8] between processor 1 and 2. Bit [9] between processor 1 and 3. Bit [10] between processor 2 and 3. Nominal (primary) first selfcheck comparator Error. Bit [11] between processor 1 and 2. Bit [12] between processor 1 and 3. Bit [13] between processor 2 and 3. First Selfcheck Voter Error. Bit [14] Selfcheck Voter Error. First Uncorrectable ECC Error. Bit [15] Uncorrectable Error from PMU RAM ECC. |
| Reserved | 7:4 | roRead-only | 0x0 | reserved |
| N_Sleep_Rst | 3 | roRead-only | 0x0 | Nominal (primary) fault detection. PMU Sleep Instruction Response. 0: causes the PMU CPUs to go to sleep. 1: causes the PMU CPUs to reset. Read-only. |
| N_LSFail | 2:0 | roRead-only | 0x0 | Nominal (primary) fault detection. First lockstep mismatch. Bit [0] processors 1 and 2. Bit [1] processors 1 and 3. Bit [2] processors 2 and 3. |