MASK_DATA_4_LSW (GPIO) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MASK_DATA_4_LSW (GPIO) Register Description

Register NameMASK_DATA_4_LSW
Offset Address0x0000000020
Absolute Address 0x00FF0A0020 (GPIO)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionMaskable Output Data (GPIO Bank4, EMIO, Lower 16bits)

This register operates in exactly the same manner as MASK_DATA_0_LSW, except that it controls the lower 16 bits of bank4, which corresponds to EMIO[47:32].

MASK_DATA_4_LSW (GPIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MASK_4_LSW31:16woWrite-only0x0Operation is the same as MASK_DATA_0_LSW [MASK_0_LSW]
DATA_4_LSW15:0rwNormal read/write0x0Operation is the same as MASK_DATA_0_LSW [DATA_0_LSW]