LSR (FTM) Register Description
| Register Name | LSR |
|---|---|
| Offset Address | 0x0000000FB4 |
| Absolute Address | 0x00FE9D0FB4 (CORESIGHT_SOC_FTM) |
| Width | 3 |
| Type | roRead-only |
| Reset Value | 0x00000003 |
| Description | Lock Status Register |
LSR (FTM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| 8BIT | 2 | roRead-only | 0x0 | Set to 0 since FTM implements a 32-bit lock access register |
| STATUS | 1 | roRead-only | 0x1 | Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): When a lower 2GB address is used to read this register, this bit indicates whether FTM is in locked state (1= locked, 0= unlocked). - PADDRDBG31=1 (upper 2GB): always returns 0. |
| IMP | 0 | roRead-only | 0x1 | Read behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): always returns 1, meaning lock mechanism are implemented. - PADDRDBG31=1 (upper 2GB): always returns 0, meaning lock mechanism is NOT implemented. |