LOC_PWR_STATE (PMU_LOCAL) Register Description
| Register Name | LOC_PWR_STATE |
|---|
| Offset Address | 0x0000000100 |
|---|
| Absolute Address |
0x00FFD60100 (PMU_LOCAL)
|
|---|
| Width | 32 |
|---|
| Type | mixedMixed types. See bit-field details. |
|---|
| Reset Value | 0x003FFCBF |
|---|
| Description | Power Island Status. |
|---|
This register provides the Power up Status for all islands within the PS. 0: powered-off. 1: powered-up. The register maintains its contents during a System Reset.
LOC_PWR_STATE (PMU_LOCAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:22 | roRead-only | 0x0 | reserved |
| USB1 | 21 | rwNormal read/write | 0x1 | USB Controller 1. |
| USB0 | 20 | rwNormal read/write | 0x1 | USB Controller 0. |
| OCM_Bank3 | 19 | rwNormal read/write | 0x1 | OCM bank 3. |
| OCM_Bank2 | 18 | rwNormal read/write | 0x1 | OCM bank 2. |
| OCM_Bank1 | 17 | rwNormal read/write | 0x1 | OCM bank 1. |
| OCM_Bank0 | 16 | rwNormal read/write | 0x1 | OCM bank 0. |
| TCM1B | 15 | rwNormal read/write | 0x1 | RPU core 1, TCM_B. |
| TCM1A | 14 | rwNormal read/write | 0x1 | RPU core 1, TCM_A. |
| TCM0B | 13 | rwNormal read/write | 0x1 | RPU core 0, TCM_B. |
| TCM0A | 12 | rwNormal read/write | 0x1 | RPU core 0, TCM_A. |
| R5_1 | 11 | rwNormal read/write | 0x1 | RPU core1. |
| R5_0 | 10 | rwNormal read/write | 0x1 | RPU core 0. |
| Reserved | 9 | roRead-only | 0x0 | reserved |
| Reserved | 8 | roRead-only | 0x0 | reserved |
| L2 | 7 | rwNormal read/write | 0x1 | APU L2 Cache. |
| Reserved | 6 | roRead-only | 0x0 | reserved |
| GPU_PP1 | 5 | rwNormal read/write | 0x1 | GPU Pixel Processor 1. |
| GPU_PP0 | 4 | rwNormal read/write | 0x1 | GPU Pixel Processor 0. |
| ACPU3 | 3 | rwNormal read/write | 0x1 | APU core 3. |
| ACPU2 | 2 | rwNormal read/write | 0x1 | APU core 2. |
| ACPU1 | 1 | rwNormal read/write | 0x1 | APU core 1. |
| ACPU0 | 0 | rwNormal read/write | 0x1 | APU core 0. |