L3_TM_AUX_0 (SERDES) Register - L3_TM_AUX_0 (SERDES) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

L3_TM_AUX_0 (SERDES) Register Description

Register NameL3_TM_AUX_0
Offset Address0x000000D0CC
Absolute Address 0x00FD40D0CC (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L3_TM_AUX_0 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_AUX_0_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
bit_0 7rwNormal read/write0x0Value generated by PCW.
bit_1 6rwNormal read/write0x0Value generated by PCW.
bit_2 5rwNormal read/write0x0Value generated by PCW.
bit_3 4rwNormal read/write0x0Value generated by PCW.
bit_4 3rwNormal read/write0x0Value generated by PCW.
bit_5 2rwNormal read/write0x0Value generated by PCW.
bit_6 1rwNormal read/write0x0Value generated by PCW.
bit_7 0rwNormal read/write0x0Value generated by PCW.