L1_TM_RST_DLY (SERDES) Register Description
| Register Name | L1_TM_RST_DLY |
|---|---|
| Offset Address | 0x00000059A4 |
| Absolute Address | 0x00FD4059A4 (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L1_TM_RST_DLY (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TM_RST_DLY_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| apb_rst_dly | 7:0 | rwNormal read/write | 0x0 | Value generated by PCW. |