I_STS (AFIFM) Register Description
| Register Name | I_STS |
|---|---|
| Offset Address | 0x0000000E00 |
| Absolute Address |
0x00FD360E00 (AFIFM0) 0x00FD370E00 (AFIFM1) 0x00FD380E00 (AFIFM2) 0x00FD390E00 (AFIFM3) 0x00FD3A0E00 (AFIFM4) 0x00FD3B0E00 (AFIFM5) 0x00FF9B0E00 (AFIFM6) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interrupt Status Register |
This register holds the contents of the raw, pre-masked interrupt status bit. Even if a mask bit is set, S/W could still read this sticky bit to see if any event actually occurred. This register requires a specific write=1 to clear its contents. Writes=0 are ignored.
I_STS (AFIFM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | razRead as zero | 0x0 | RESERVED. Return 0 when read. Writes ignored. Software Driver name: XQSPIPS_IXR_RXFULL |
| INVALID_APB | 0 | wtcReadable, write a 1 to clear | 0x0 | Indicates that an APB (register) access has occured to an unimplemented space (there is no register at that location). |