I_MSII_CONTROL (AXIPCIE_MAIN) Register Description
| Register Name | I_MSII_CONTROL |
|---|---|
| Offset Address | 0x0000000308 |
| Absolute Address | 0x00FD0E0308 (AXIPCIE_MAIN) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Ingress PCI Express Received MSI Interrupt Translation - Control |
I_MSII_CONTROL (AXIPCIE_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:21 | roRead-only | 0x0 | |
| i_msii_size | 20:16 | rwNormal read/write | 0x0 | Size of this translation window, expressed as 2^(msii_size_offset+msii_size). Constrained by the i_msii_size_max and i_msii_size_offset fields. |
| i_msii_status_enable | 15 | rwNormal read/write | 0x0 | |
| Reserved | 14:1 | roRead-only | 0x0 | |
| i_msii_enable | 0 | rwNormal read/write | 0x0 | Translation Enable. The translation is hit when both of the following are true: * i_msii_enable == 1 * i_msii_src_base[63:(12+i_msii_size)] == AXI Address[63:(12+i_msii_size)] |