ITC_CPU_IRQ_MSK (VCU_ENC_TOP) Register - ITC_CPU_IRQ_MSK (VCU_ENC_TOP) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

ITC_CPU_IRQ_MSK (VCU_ENC_TOP) Register Description

Register NameITC_CPU_IRQ_MSK
Offset Address0x0000009104
Absolute Address 0x00A0009104 (VCU_ENCODE)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionCPU Interrupt Mask

ITC_CPU_IRQ_MSK (VCU_ENC_TOP) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8rwNormal read/write0x0Reserved
Extirq1InterruptMask 7rwNormal read/write0x0EXTIRQ1 interrupt mask:
0: disable EXTIRQ1 interrupt source
1: enable EXTIRQ1 interrupt source
Extirq0InterruptMask 6rwNormal read/write0x0EXTIRQ0 interrupt mask:
0: disable EXTIRQ0 interrupt source
1: enable EXTIRQ0 interrupt source
Rresp1InterruptMask 5rwNormal read/write0x0RRESP1 interrupt mask:
0: disable RRESP1 interrupt source
1: enable RRESP1 interrupt source
Bresp1InterruptMask 4rwNormal read/write0x0BRESP1 interrupt mask:
0: disable BRESP1 interrupt source
1: enable BRESP1 interrupt source
Rresp0InterruptMask 3rwNormal read/write0x0RRESP0 interrupt mask:
0: disable RRESP0 interrupt source
1: enable RRESP0 interrupt source
Bresp0InterruptMask 2rwNormal read/write0x0BRESP0 interrupt mask:
0: disable BRESP0 interrupt source
1: enable BRESP0 interrupt source
Reserved 1rwNormal read/write0x0Reserved
McuToCpuInterruptMask 0rwNormal read/write0x0MCU-to-CPU interrupt mask:
0: disable MCU-to-CPU interrupt source
1: enable MCU-to-CPU interrupt source