| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:8 | razRead as zero | 0x0 | Return 0 when read |
| Extirq1InterruptClear | 7 | woWrite-only | 0x0 | EXTIRQ1 interrupt clear: writing 1 into this bit acknowledges and clears the EXTIRQ1 interrupt source (generated by the AXI master port 1 EXTIRQ input). Read accesses return 0. |
| Extirq0InterruptClear | 6 | woWrite-only | 0x0 | EXTIRQ0 interrupt clear: writing 1 into this bit acknowledges and clears the EXTIRQ0 interrupt source (generated by the AXI master port 0 EXTIRQ input). Read accesses return 0. |
| Rresp1InterruptClear | 5 | woWrite-only | 0x0 | RRESP1 interrupt clear: writing 1 into this bit acknowledges and clears the RRESP1 interrupt source (generated by the AXI master port 1 RRESP input). Read accesses return 0. |
| Bresp1InterruptClear | 4 | woWrite-only | 0x0 | BRESP1 interrupt clear: writing 1 into this bit acknowledges and clears the BRESP1 interrupt source (generated by the AXI master port 1 BRESP input). Read accesses return 0. |
| Rresp0InterruptClear | 3 | woWrite-only | 0x0 | RRESP0 interrupt clear: writing 1 into this bit acknowledges and clears the RRESP0 interrupt source (generated by the AXI master port 0 RRESP input). Read accesses return 0. |
| Bresp0InterruptClear | 2 | woWrite-only | 0x0 | BRESP0 interrupt clear: writing 1 into this bit acknowledges and clears the BRESP0 interrupt source (generated by the AXI master port 0 BRESP input). Read accesses return 0. |
| Reserved | 1 | razRead as zero | 0x0 | Return 0 when read |
| McuToCpuInterruptClear | 0 | woWrite-only | 0x0 | MCU-to-CPU interrupt clear: writing 1 into this bit acknowledges and clears the MCU-to-CPU interrupt source (generated by the MCU using the INTERRUPT_MCU2CPU global hardware register). Read accesses return 0. |