ITATBMDATA0 (ETR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

ITATBMDATA0 (ETR) Register Description

Register NameITATBMDATA0
Offset Address0x0000000ED0
Absolute Address 0x00FE970ED0 (CORESIGHT_SOC_ETR)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionThe Integration Test ATB Master Data Register 0 enables control of the ATDATAM output of the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior.

ITATBMDATA0 (ETR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ATDATAMBit12716woWrite-only0Control the value of ATDATAM[127] output of TMC
ATDATAMBit11915woWrite-only0Control the value of ATDATAM[119] output of TMC
ATDATAMBit11114woWrite-only0Control the value of ATDATAM[111] output of TMC
ATDATAMBit10313woWrite-only0Control the value of ATDATAM[103] output of TMC
ATDATAMBit9512woWrite-only0Control the value of ATDATAM[95] output of TMC
ATDATAMBit8711woWrite-only0Control the value of ATDATAM[87] output of TMC
ATDATAMBit7910woWrite-only0Control the value of ATDATAM[79] output of TMC
ATDATAMBit71 9woWrite-only0Control the value of ATDATAM[71] output of TMC
ATDATAMBit63 8woWrite-only0Control the value of ATDATAM[63] output of TMC
ATDATAMBit55 7woWrite-only0Control the value of ATDATAM[55] output of TMC
ATDATAMBit47 6woWrite-only0Control the value of ATDATAM[47] output of TMC
ATDATAMBit39 5woWrite-only0Control the value of ATDATAM[39] output of TMC
ATDATAMBit31 4woWrite-only0x0Control the value of ATDATAM[31] output of TMC
ATDATAMBit23 3woWrite-only0x0Control the value of ATDATAM[23] output of TMC
ATDATAMBit15 2woWrite-only0x0Control the value of ATDATAM[15] output of TMC
ATDATAMBit7 1woWrite-only0x0Control the value of ATDATAM[7] output of TMC
ATDATAMBit0 0woWrite-only0x0Control the value of ATDATAM[0] output of TMC