ITATBMCTR0 (ETR) Register Description
| Register Name | ITATBMCTR0 |
|---|---|
| Offset Address | 0x0000000EDC |
| Absolute Address | 0x00FE970EDC (CORESIGHT_SOC_ETR) |
| Width | 32 |
| Type | woWrite-only |
| Reset Value | 0x00000000 |
| Description | The Integration Test ATB Master Interface Control Register 0 enables control of the ATBYTESM, AFREADYM and ATVALIDM outputs of the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior. |
ITATBMCTR0 (ETR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ATBYTESM | 9:8 | woWrite-only | 0 | Control the value of ATBYTESM output from TMC. The value written to this field is driven on the ATBYTESM output of the TMC. |
| AFREADYM | 1 | woWrite-only | 0x0 | Set the value of AFREADYM output |
| ATVALIDM | 0 | woWrite-only | 0x0 | Set the value of ATVALIDM output |