IDR (QSPI) Register Description
| Register Name | IDR |
|---|---|
| Offset Address | 0x000000000C |
| Absolute Address | 0x00FF0F000C (QSPI) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interrupt Disable |
Writing a 1 to this register sets the corresponding bits of the interrupt mask register. 0: no effect. 1: disable the interrupt (unmask = 0). Software Driver name: XQSPIPS_IDR
IDR (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:9 | roRead-only | 0x0 | reserved |
| TXFIFO_EMPTY | 8 | woWrite-only | 0x0 | TX FIFO Empty interrupt disable |
| Reserved | 7 | woWrite-only | 0x0 | reserved |
| TX_FIFO_underflow | 6 | woWrite-only | 0x0 | TX FIFO underflow disable Software Driver name: XQSPIPS_IXR_TXUF |
| RX_FIFO_full | 5 | woWrite-only | 0x0 | RX FIFO full disable Software Driver name: XQSPIPS_IXR_RXFULL |
| RX_FIFO_not_empty | 4 | woWrite-only | 0x0 | RX FIFO not empty disable Software Driver name: XQSPIPS_IXR_RXNEMPTY |
| TX_FIFO_full | 3 | woWrite-only | 0x0 | TX FIFO full disable Software Driver name: XQSPIPS_IXR_TXFULL |
| TX_FIFO_not_full | 2 | woWrite-only | 0x0 | TX FIFO not full disable Software Driver name: XQSPIPS_IXR_TXOW |
| Reserved | 1 | woWrite-only | 0x0 | reserved |
| RX_OVERFLOW | 0 | woWrite-only | 0x0 | Receive Overflow interrupt disable Software Driver name: XQSPIPS_IXR_RXOVR |